Education/Teaching/Working History

Education

• Ph.D. in Electrical Engineering and Computer Science (Sept. 2004-Feb.2010)
  Massachustts Institute of Technology (MIT), Cambridge, MA, USA
  Advisor: Vladimir Stojanović
  Thesis: "Equalized On-Chip Interconnect: Modeling, Analysis, and Design." (thesis, talk)
  Research area: a network-on-a-chip using equalization (system), high speed low power I/O circuit design (circuit design), and computer-aided-design for interconnects (CAD).
  Group link: http://www.rle.mit.edu/isg/default.htm
• M.S. in Electrical Engineering and Computer Science (Sept. 2002-Feb.2004)
  Massachustts Institute of Technology (MIT), Cambridge, MA, USA
  Advisor: Arvind
  Thesis: "An Effcient Buffer Management for Cachet." (thesis)
  Group link: http://csg.csail.mit.edu/index.html
  Research area: computer architecture, formal verification, and high level hardware synthesis.
• B.S. in Electronic and Electrical Engineering (Mar. 1997-Aug.2002)
  Pohang Univerity of Science and Technology (POSTECH), Pohang, Korea
  GPA: 4.04/4.3
  Summa Cum Laude

Teaching Experience

• TA. 6.002 Electronic Circuits (Fall.2004)
  Massachustts Institute of Technology (MIT), Cambridge, MA, USA
  Introduction to circuits and electronics cource for undergraduate. Topics include principles of circuit design such as RLC circuits, small signal analysis, etc.
• Head TA. 6.002 Electronic Circuits (Spring.2006)
  Massachustts Institute of Technology (MIT), Cambridge, MA, USA
  Principle of circuits and electronics cource for undergraduate. Managemental help in addition to regular TA role: tutorial session, lab instruction, and homework and quiz assessment. Managemental help includes a weekely report on statistical student progress, session and lab organization, as well as overall class/exam/quiz organization.

Working Experience

• Summer Intern (Summers of 2006 and 2007)
  IBM TJ Watson Research Center, Yorktown Heights, NY USA
  Designed and developed high-speed I/O architectures and circuits (DFE-IIR) for silicon carrier package technology.
• Summer Intern (Summer of 2009)
  Intel Corporation, Hillsboro, OR, USA
  Research on the future interconnect circuits (confidential in detail).
• Senior Engineer (Mar. 2010-present)
  Intel Corporation, Hillsboro, OR, USA
  Research on the future interconnect circuits (confidential in detail).