Research

Future Research Interest

1. Comprehensive Interconnect Scaling
Circuit-system-interconnect cross-layer design and optimization for emerging scaled interconnects such as through-silicon-via (TSV), silicon carrier [2], and on-chip network interconnects [1,3-5].

    Direction of future interconnect scaling

2. Concurrent Device-Circuit-System Design Automation Methodology
Design automation methodology for device-circuit-system co-optimization [5] and synthesis by combining analog circuit optimization [3, 4] from device level with high-level system design automation method.

    CAD for system+circuit+device joint development

3. Post-CMOS Electronics
System-circuit-device cross-layer study and evaluation for the emerging post-CMOS elements such as nanophotonics, MEMS switch, carbon nano tube, grapheme, and nanowire.

    cross-layer study for post CMOS technology

4. Emerging Diversified System Application
Invention of new electronic circuits and systems for health care equipments, pervasive computing systems, mobile computation units, lab-on-a-chip equipments, and scientific nano-/bio-measurement tools.
Emerging applications by combining different fields






Selected Past Research

1. Circuit Design
[1] Byungsub Kim and Vladimir Stojanović, “An Energy-Efficient Equalized Transceiver for RC-dominant Channels,” IEEE Journal of Solid-State Circuits, vol. 45, issue 6, pp. 1186-1197, June 2010.
  • Improved data rate density and energy efficiency using equalizing transceiver circutis for a 10mm On-chip Interconnect.
    • operated 4-6Gb/s/ch and 2-3Gb/s/um over a >40dB* channel loss.
      • >40dB and low power operation is very rare.
    • energy efficiency was about 0.4-0.6pJ/b
  • Charge-injection equalization transmitter architecture is introduced for the first time
    • For on-chip interconnect appplication, energy efficiency is imporved by 2x, 2x, and 4x compared to current switch, voltage mode, and current mode driver, respectively.
    • For 50Ohm off-chiop interconnect application, energy efficiency is improved by 2x, 3x, and 8x compared to current switch, voltage mode, and current mode driver, respectively.
    • Transmitter's resolution requirement is improved by 10x. This relaxation of resolution requirement enables >40dB-operation at cheap power and hardware cost.
      • Relaxation of resolution requirement is analyzed by eye-sensitivity analysis and demonstrated in experiment.
    • Charge-injection scheme alows cheap static pre-distortion
  • Static pre-distortion technique is introduced for the first time.
    • Static pre-distortion utilizes non-linear circuits as a linear feed forward equalizing (FFE) transmitter at cheap cost.
    • Current source circuits are replaced with 5x smaller (in width) inverters for FFE operation.
    • Eye is improved by pre-distortion technique
      • With conventional transmitter circuits
        • eye closes in theoretical calculation without pre-distortion
      • With charge-injection transmitter circuits
        • eye is 30% improved by pre-distortion in simulation
  • Trans-impedance amplifing receiver is suggested in this application to improve signal amplitude by 3x at 50% smaller static power cost for the same bandwidth.
  • 2009 ADI Outstanding Student Designer Award from MIT
  • 2009 ISSCC highlight
[2] Byungsub Kim, Young Liu, Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, “A 10-Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 64nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, issue 12, pp. 3526-3538, December 2009 [Invited].
  • An equalizing transceiver is developed, designed and tested for a low power and high speed data communication through emerging on-package interconnect (system in package application) called silicon carrier.
  • A decision feedback equalization (DFE) with infinite impulse reponse (IIR) filter, called DFE-IIR, is designed to reduce hardware (DFE-tap count) and power cost.
  • 1st DFE-tap circuit's critical delay is improved by direct current comparator to allow a low power direction feedback at 10Gb/s
  • Receiver sensitivity and timing margin for the critical path is improved by doulbe regenerating latches. Double regenerating latches provided CMOS-to-CMOL voltage level conversion, improving tail current's accuracy.
  • Analysis and suggestion of termination policy for the the emerging silicon carrier channel.
  • A major award will be given to this paper in 2011.
  • ISSCC paper received Beatrice Winner Award for the Editorial Excellence in 2009.
  • ISSCC 2009 highlight
  • Major contents in this paper are applied for US and International patents.
2. Mixed-Signal Circuit Design Automation
[3] Byungsub Kim and Vladimir Stojanović, “Equalized Interconnect for On-Chip Network: Modeling and Optimization Framework,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, November. 2007, pp. 552-559.
  • A modeling and framework methology is suggested for network-on-a-chip (NoC) interconnects using a low power equalization technique.
  • Cross-layer design automation direction including mixed-signal circuit is suggested.
  • Modeling, analysis, approximation, and algorithms for fast and easy estimation for equalized interconnects.
  • 30,000 times faster estimation compared to SPICE simulation for link metric computation.
  • equalized interconnects are better than repeated interconnects in comparison.
  • equalized interconnect toolbox is developed and being prepared for source code open.
3. System-Circuit Cross-layer Design for Network-on-a-chip (NoC)
[4] Byungsub Kim and Vladimir Stojanović, “Characterization of Equalized and Repeated Interconnects for NoC Applications,” IEEE Design and Test of Computers, vol. 25, issue 5, pp. 430-439, October 2008 [Invited].
  • NoC interconnect metrics are compared when optimized using repeater insertion and equalization techniques in aggressively scaled 32nm technoloy.
  • A simple approximation method is suggested to evaluate delay-power-energy 3-dimensional trade-off cruve or repeated interconnects.
[5] Ajay Joshi, Byungsub Kim, and Vladimir Stojanović, “Designing Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,” in Proc. of the 17th IEEE High-Performance Interconnects, August 2009, pp. 3-12.
  • NoC metrics are compared when equalized interconnects and repeated interconnects are used by using event-driven NoC simulator and equalized interconnect toolbox as a system-circuit cross-layer design approach.
  • Various combination of NoC topologies and interconnect types (equalized and repeated interconnects) are evaluated and compared.
  • An example of the possible system-circuit cross-alyer design automation.
홈
피드 구독하기: 글 (Atom)