[1] Byungsub Kim, "An Efficient Buffer Management for Cachet," Master thesis, Dept. EECS, MIT, Cambridge, MA, 2004.
[2] Byungsub Kim, "Equalized On-Chip Interconnect: Modeling, Analysis, and Design," Ph.D. dissertation, Dept. EECS, MIT, Cambridge, MA, 2010. [talk] [MIT EECS Jin-Au Kong Outstanding Doctoral Thesis Honorable Mentions, May 2011]
Conference
[1] Byungsub Kim, Soumyajit Mandal, and Rahul Sarpeshkar, “Power-Adaptive Operational Amplifier with Positive Feedback Self-Biasing,” in IEEE Int. Sym. on Circuits and Systems, May 2006. [Selected 5 tape-outs from a class project].
[2] Byungsub Kim and Vladimir Stojanović, “Equalized Interconnect for On-Chip Network: Modeling and Optimization Framework,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 2007.
[3]* Yong Liu, Byungsub Kim (equal contributor – please refer journal *), Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009 [ISSCC Beatrice Winner Award for Editorial Excellence, ISSCC 2009 highlight ].
[4] Byungsub Kim and Vladimir Stojanović, “A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS Technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , Feb. 2009 [ADI Outstanding Student Designer Award, ISSCC 2009 highlight ].
[5] Sanquan Song, Byungsub Kim, and Vladimir Stojanović , “A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion,” in IEEE Sym. VLSI Circuits Dig. Tech. Papers, June 2009.
[6] Ajay Joshi, Byungsub Kim, and Vladimir Stojanović, “Designing Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,” in Proc. IEEE Hot Interconnects, Aug. 2009.
Journal
[1] Byungsub Kim and Vladimir Stojanović , “Characterization of Equalized and Repeated Interconnects for NoC Applications,” IEEE Design and Test of Computers, Oct. 2008. [invited]
[2]* Byungsub Kim, Yong Liu (equal contributor – please refer conference *), Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, “A 10-Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” IEEE Journal of Solid-State Circuits, Dec. 2009 [invited, 2009 JSSC Best Paper Award].
[3] Byungsub Kim and Vladimir Stojanović, “An Energy-efficient Equalized Transceiver for RC-dominant Channels,” IEEE Journal of Solid-State Circuits, June 2010.
Workshop
[1] Byungsub Kim and Arvind, “BCachet: Efficient Buffer Management for Cachet,” Boston Area Architecture Workshop , Jan. 2005.
[2] Byungsub Kim and Vladimir Stojanović, “Energy Efficient Wireline Communication Over RC-dominant Channels,” CMOS Emerging Technologies, Sept. 2009 [invited].
[3] Byungsub Kim and Vladimir Stojanović, “Future State-of-the-Art Electrical Interconnect,” Workshop on the Interaction between Nanophotonic Devices and Systems (co-located with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture), Dec. 2010 [invited].
Patent
[1]* Byungsub Kim and John F. Bulzacchelli, “Circuits and methods for DFE with reduced area and power consumption” [International patent pending].
[2]* John F. Bulzacchelli and Byungsub Kim, “Circuits and methods for DFE with reduced area and power consumption” [US patent pending].
Software
[2] Byungsub Kim and Vladimir Stojanović, “Equalized Interconnect for On-Chip Network: Modeling and Optimization Framework,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 2007.
[3]* Yong Liu, Byungsub Kim (equal contributor – please refer journal *), Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009 [ISSCC Beatrice Winner Award for Editorial Excellence, ISSCC 2009 highlight ].
[4] Byungsub Kim and Vladimir Stojanović, “A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS Technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , Feb. 2009 [ADI Outstanding Student Designer Award, ISSCC 2009 highlight ].
[5] Sanquan Song, Byungsub Kim, and Vladimir Stojanović , “A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion,” in IEEE Sym. VLSI Circuits Dig. Tech. Papers, June 2009.
[6] Ajay Joshi, Byungsub Kim, and Vladimir Stojanović, “Designing Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,” in Proc. IEEE Hot Interconnects, Aug. 2009.
Journal
[1] Byungsub Kim and Vladimir Stojanović , “Characterization of Equalized and Repeated Interconnects for NoC Applications,” IEEE Design and Test of Computers, Oct. 2008. [invited]
[2]* Byungsub Kim, Yong Liu (equal contributor – please refer conference *), Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, “A 10-Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” IEEE Journal of Solid-State Circuits, Dec. 2009 [invited, 2009 JSSC Best Paper Award].
[3] Byungsub Kim and Vladimir Stojanović, “An Energy-efficient Equalized Transceiver for RC-dominant Channels,” IEEE Journal of Solid-State Circuits, June 2010.
Workshop
[1] Byungsub Kim and Arvind, “BCachet: Efficient Buffer Management for Cachet,” Boston Area Architecture Workshop , Jan. 2005.
[2] Byungsub Kim and Vladimir Stojanović, “Energy Efficient Wireline Communication Over RC-dominant Channels,” CMOS Emerging Technologies, Sept. 2009 [invited].
[3] Byungsub Kim and Vladimir Stojanović, “Future State-of-the-Art Electrical Interconnect,” Workshop on the Interaction between Nanophotonic Devices and Systems (co-located with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture), Dec. 2010 [invited].
Patent
[1]* Byungsub Kim and John F. Bulzacchelli, “Circuits and methods for DFE with reduced area and power consumption” [International patent pending].
[2]* John F. Bulzacchelli and Byungsub Kim, “Circuits and methods for DFE with reduced area and power consumption” [US patent pending].
Software